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Documents

These are all SNES related, some written by me, other written by those before me. If you have SNES programming related questions that are not answered in the documents below, feel free to ask me. I might not be able to give you an answer, but I'll gladly try to. Check out Emulation Programmer's Resource or Zophar's Domain for more.

Unique
ZSNES Savestate Format ZsKnight ZsKnight was nice enough to send this to me to help get BgMapper going. In case anybody else can get use out of this, here it is. This only accounts for 65816 registers, all PPU regs, palette, VRAM, and memory, nothing on the SPC, FX, or SA-1 chip.
ZSNES Savestate SPC Format _Demo_ Here is the format for the SPC portion of the savestate (beyond 199699 bytes)
SNES graphics Peekin
1998.5.28
Written to explain how SNES tiles were stored. I wrote this one before the existance of this page, before "Peekin", before ZSNES had its superior fame...
Zelda Decompression Routine Peekin Comments on the disassembly of the routine that decompresses graphics. Sames as Mario World compression and similr to Pokemon Gold & Silver.
Fx chip graphics Peekin What little I've found out about how graphics for the fx chip are stored in games such as "StarFox" and "Yoshi's Island". There seems to be virtually no documentation around about the fx chip. If anybody has some real info, please send it to me :)
Pseudo 16x16 tiles Peekin A little bit to explain how 16x16 tiles are built from 4 smaller 8x8 tiles using tile tables.
Main screen/sub screen layering

Illustration
Peekin Ever been curious about how the SNES scene is layered? Probably not, but here is the info anyway.
TileView locations Peekin Some interesting spots in savestates or ROMs with tilemaps that you might want to check out with TileView.
 
More good ones
SNES Register Map Nintendo? Extensive list of SNES registers.
SPC-700 APU Manual Ledi Great explanation of the SPC-700 chip with complete register and opcode listings. (I added missing diagrams and section 8)
SNES Memory Organization SiMKiN Tells how memory banks are organized in both low and high ROM modes.
BRR encoding Butcha Explanation of the SPC-700's BRR sample compression.
SNES Kart 1.6 DiskDude Details on the SNES cartridge, PIN layouts, addressing schemes, and header information.
65c816 Processor info GTE Opcodes, registers, addressing modes...
More 65c816 info (unknown) Opcodes, registers, addressing modes...
SNES Initialization Source (unknown) Shows how to initialize the SNES registers to defaults and how to plot characters or strings to VRAM.
SPC-700 Source AntiTrack Decompiled source of an SPC-700 routine for playing music.

2003 PeekinSoft